New ContributorSDI II Core | Error in the synthesis stage (Quartus 20.1)
Hello! In our project we use the Intel SDI IP Core and transceivers. In the simulation stage it works properly but in the synthesis stage we're got the next error:
This json file has patch that is created by the Quartus itself. We don't understand why it can't do it. Do you have any ideas?
Software version is Quartus Prime Pro 20.1, SDI IP Core is used in the Evaluation mode.
Device Cyclone 10 GX: 10CX220YF780E5G.
Hi,
As I understand it, you are observing some compilation issue with the SDI II IP in C10GX devices. As I understand it, the IP is able to generate example design from the IP Catalog Editor. Just wonder if you have had a chance to try generating the example design and run through the compilation to see if similar issue persist?
If you observe similar issue with example design in Q20.1Pro, it would be great if you could help to try with Q19.4Pro to see if similar issue exist to help isolating Quartus version dependent issue.
Please let me know if there is any concern. Thank you.
