SDC with combinatorial circuit

Please download the TimeQuest User Guide from the Altera Wiki and have a look at page 61 onwards.

Best regards,

Ben

For a quick reference:

create_clock -period 20.0 -name ext_clk_virt

set_input_delay -clock ext_clk_virt -max 2.0 [get_ports A*]

set_output_delay -clock ext_clk_virt -max 3.0 [get_ports Y*]

That's the basic syntax. It may seem dumb at first, as why would you use three lines to do what can be done in one. First, there's nothing wrong with what you have so if you like it, keep it. But what I have above says there is a board level clock running at 20ns. The Tco + board_delay of the upstream device is 2ns. The Tsu + board_delay of the downstream device is 3.0ns. So the setup relationship between these two external registers is 10ns, 5.0ns of it is chewed up externally. What does that leave for the FPGA delays, a 15ns delay to get data through. This actually is a better representation of what the timing analysis is, rather than having all these calculations on a notebook that doesn't stay with the design. (I minimally recommend putting your calculations in a comment next to each constraint).

Technically though, they will both give the same results, and for combinatorially delays I see how what you have can be easier. My only argument is that for the registered I/O ports, you should use set_input_delay and set_output_delay constraints, and once you understand them, this other method will keep consistency.

Rysc's suggested method will also result in a better organized Timing Report, and will make it a lot easier for you to use report timing like this: "report_timing -from [get_clocks ext_clk_vir] -to [get_clocks ext_clk_vir]"

Basically, Static Timing Analysis is at the end of the day, a clock transfer analysis tool, so it really wants to do everything in terms of clocks (internal or external to your FPGA).