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Altera_Forum
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15 years ago

SDC with combinatorial circuit

I'm a beginner on TimeQuest and .sdc files. I'm trying to constraint a combinatorial circuit. I would use: set_max_delay -from [ get_ports A*] -to [ get_ports Y*] 15.00 I also heard tha...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Rysc's suggested method will also result in a better organized Timing Report, and will make it a lot easier for you to use report timing like this: "report_timing -from [get_clocks ext_clk_vir] -to [get_clocks ext_clk_vir]"

Basically, Static Timing Analysis is at the end of the day, a clock transfer analysis tool, so it really wants to do everything in terms of clocks (internal or external to your FPGA).