SDC ...NiosCpu_domain_synch.... unconstrained clock ?

This time i relay need some help to find the source of this warning message to get rid of it:

Warning: Node: SOPC_Nios2:inst|SOPC_Nios2_reset_clk_NiosCpu_domain_synch_module:SOPC_Nios2_reset_clk_NiosCpu_domain_synch|data_out was determined to be a clock but was found without an associated clock assignment.

The SDC report uncontrained paths -> clock status summary says :

Target : SOPC_Nios2:inst|SOPC_Nios2_reset_clk_NiosCpu_domain_synch_module:SOPC_Nios2_reset_clk_NiosCpu_domain_synch|data_out

Clock : *empty*

Type : Base

Status : Uncontrained

one of my sdc files has a

set_clock_groups -asynchronous -group { FPGA_CLK0

inst|the_pll_0|the_pll|altpll_component|pll|clk[0]

inst|the_pll_0|the_pll|altpll_component|pll|clk[1]

inst|the_pll_0|the_pll|altpll_component|pll|clk[2]

}

as well as another set_clock_group for each external clock input like those for the ethernet mac.

if have tried lots of set_false_path but nothing helped.

i think that need to cut a path between one clock (which one ?) and the target mentioned by the clock report.

i looked into the RTL viewer and the reported signals comes out of a DFF that is clocked by the external clock FPGA_CLK0 input that feeds the pll

if if set_false_path for ExternalClock FPGA_CLK0 and the reported signal, i get lots of uncontrained ports (as if nothing is contrained at all)

has anybody an idea or can point me to the right solution ?