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Altera_Forum's avatar
Altera_Forum
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16 years ago

SDC ...NiosCpu_domain_synch.... unconstrained clock ?

This time i relay need some help to find the source of this warning message to get rid of it: Warning: Node: SOPC_Nios2:inst|SOPC_Nios2_reset_clk_NiosCpu_domain_synch_module:SOPC_Nios2_reset_cl...
Altera_Forum's avatar
Altera_Forum
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16 years ago

has nobody an idea ?

i have this problem now with 7 different fpga projects

it is always this domain_synch data out