Hello,
"Should I have two completely separate constraints?"
- Yes, typically need to consider both the positive and negative edges separately because data is sampled on both edges of the clock.
"How do I do constraints for both positive and negative edges?"
- From my understanding, the idea roughly is like this,
- From data constraint, you need to identify the setup and hold times for the data relative to both the positive and negative edges of the clock.
- Use set_input_delay constraints to specify the setup and hold times for the data signals relative to clock edges.
- And then, you prolly need to do group and I/O contraints.
- So your SDC will have set input/output delay for positive and negative respectively
Regards,
Adzim
Contributor
