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New ContributorSDC file for clk from Native Phy
Sorry that it was a bit late on the reply,
In Timing anaylizer we can set multiple clock frequencies if you have a switch outside the FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 7.
However, since yours is related to dynamic reconfig of an PLL, What you can do is look into the example design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf download the pll_reconfig_mnc.qar see how they constrain the sdc. If there are nothing inside, means they expect customer to test it on their hardware to make sure it works.
Super ContributorSorry that it was a bit late on the reply,
In Timing anaylizer we can set multiple clock frequencies if you have a switch outside the FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 7.
However, since yours is related to dynamic reconfig of an PLL, What you can do is look into the example design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf download the pll_reconfig_mnc.qar see how they constrain the sdc. If there are nothing inside, means they expect customer to test it on their hardware to make sure it works.
