Script or Tool in Quartus 18.1 to Extract RTL File List for Xcelium
Hi,
Hello,
I am working with Quartus Prime Standard 18.1 and need to generate a file (rtl_files.f) containing all VHDL and Verilog source files used in my Quartus project. This file will be used as an RTL file list for Xcelium's xrun simulator.
Currently, I can extract file lists manually from the .qsf file, which contains set_global_assignment -name VHDL_FILE and set_global_assignment -name VERILOG_FILE entries. However, the .qsf also includes .qip (Quartus IP) files, which do not directly list the underlying Verilog/VHDL files used by the IP cores.
I need a way to extract not only the files listed directly in the .qsf but also the actual RTL files referenced inside each .qip file so that rtl_files.f includes all necessary sources for Xcelium xrun.
Could you provide guidance on:
- Any built-in Quartus commands, scripts, or tools that can generate a complete RTL file list (including files inside .qip)?
- Alternative ways to achieve this efficiently within Quartus 18.1?
I would appreciate any official documentation or recommended methods to automate this process.
Thank you for your support!
Best regards,
Itshak Chalfon