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itchalfon's avatar
itchalfon
Icon for New Contributor rankNew Contributor
9 months ago

Script or Tool in Quartus 18.1 to Extract RTL File List for Xcelium

Hi, Hello, I am working with Quartus Prime Standard 18.1 and need to generate a file (rtl_files.f) containing all VHDL and Verilog source files used in my Quartus project. This file will be used as...
Hdl
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
9 months ago

You can use the NativeLink feature (supported in Lite/Standard only) to automatically compile your design, Altera IP, simulation model libraries, and testbench.


You may checkout the user guide below on how to set up the nativelink simulation.

https://www.intel.com/content/www/us/en/docs/programmable/683080/23-1/setting-up-nativelink-simulation.html


We also have a quick start manual on how to use the Nativelink simulation flow using the Questa simulator tool.

Questa* Intel® FPGA Edition Quick-Start (Lite/Standard Edition):

https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html


Regards,

Richard Tan