Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

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Might I also add the use of source control(svn, vss, cvs,...) is a lot easier in text based designs rather than altera schematic files.

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.bdf and .bsf are text files too. Of course a diff of them will be a bit harder to read.

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And, did Altera drop it for lack of interest? I don't know AHDL and cannot offer any worthwhile comment. Just a logic/systems guy that can put together some code and get it to run. Would like your comments, especially if the similarity is undesirable. Thanks.

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Theres nothing wrong with it as a language. The big problem is lack of support from other vendors (especially as it is Altera HDL).

The problem with the language, and anything similar is that you cant get away from the problem that different vendors have slightly different technologies.

IIRC, altera registers all have an async reset input, while Xilinx prefer sync resets. Also, Altera have a reset and a preset inputs. This comes out in the code like this:

node my_reg : dffe;
my_reg.clk = clk;
my_reg.en = enable;
my_reg.reset = rst;
mr_reg.prn = something;
my_reg.d = input1 & input2;
output = my_reg.q;
etc. etc.

It also has libraries for the multipliers, fifos, memories etc etc that come from vendors. But again the problem is that the interfaces for these differ from vendor to vendor. Writing like this is forcing you to think about the target technology, rather than code that is vendor independent. In VHDL, I can create a RAM that any synethesisor should pick up and place (sorry for the VHDL, but I dont know verilog):

type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0);
signal RAM  : ram_t;
process(clk)
begin
  if rising_edge(clk) then
    if we = '1' then
      RAM(wr_addr) <= input;
    end if;
    read_addr_r <= read_addr;
  end if;
end process;
output <= RAM(read_addr_r); --for a registered read.

With this code, I can run it through any synthesisor without modifying the code, because it defines a behaviour that matches the behaviour for a ram, without worrying about different vendors port names.

I believe Altera is going to or already has 'orphaned' AHDL, as it looks they are developing all their new IP in Verilog?

We used to do a lot in AHDL (being a concise 'low level' language in comparison with verbose VHDL and others), but have switched to VHDL mainly because that's what the younger developers learn at the university (over here in Europe).

There are so many concerns that the situation seems hopeless except for the fact that there are successful projects So ...

1) There is a seed that contains the gist of function and likely a block diagram .. just general goes in, comes out stuff, with an idea of data manipulation.

2) At this stage, there is not really enough detail to effectively do design entry, but it would be nice to have a way to apply some inputs and see some output.

3) There are controls, registers, and memory. and each has a name. The regs and memory hold data. Boolean combinations of controls sampled by a clock control the data movement among the regs and memory.

4) There is no need to draw lines to connect the logic, do it with name.block resolution Coding style for HDL is unnecessary. Everything is text so a text editor can be used to select the appropriate text for the level of function detail for each block in a folder. Here is a place where source control can be used to see exactly what is different for each level of detail. If the interface between two blocks changed, then both blocks have to be at compatible levels.

5) The function can be simulated to the level of detail where there is value added by doing detailed design entry with the tool and vendor of choice.

6) RTL applies to programs as well as hardware and this methodology as well. Register contents are transferred directly or combined by operators during the transfer. It should be possible to generate internal RTL syntax to get the netlist which is common to all forms of design entry and serves as the graphic image of the logic, but that would bypass synthesis, placement, and routing which which require conventional design entry.

7) Is it reasonable for young engineers to gain experience by using their HDL skills in the design entry and gain experience in looking at RTl/netlists and relating that back to the intended logic implementation?

8) Now the sticky questions. This would be a tool independent of vendors. Who would own and support it? Will anyone try it out on some simple little design?

I wonder if your question was answered. Seems like HDL has the momentum. A big reason is that it is a standard across the industry. Also, the tools are written by people who are not concerned about path delay and clock domains. Even when we used schematic entry, the placement and routing used a sort of HDL to map from logic block to physical block. Our logic diagrams required placement and routing for printing as well as placement and routing for wiring. Text input is the natural for program data entry and the net list view does show a schematic. HDL does work, just not too efficiently.

I have a simulator prototype attached along with a short description of the input syntax and a test case that initializes a couple of registers and moves some bit fields from one to the other. The control logic input is Boolean rather than if/else. The register assignments controlled by each clock(domain) follow the clock definition in the text input.

The .exe is in the .zip and the syntax description and test case example are in the .txt.

Enter the electronic design world. I've designed (mostly digital) circuits in the eighties, using schematic entry. Then I return to digital design these days and find that schematic entry is frowned upon, and using VHDL/Verilog is deemed "more professional".

There are some religious issues, converts would say "more professional".

Can someone explain to me why schematic entry (which, from a pure programming standpoint could be considered a 4th generation entry-tool) is considered inferior to VHDL/Verilog (which, from a pure programming standpoint, could be considered 3rd generation entry-tools)?

I've looked at VHDL/Verilog, and even though they work for me, I find that they make it more difficult for me to envision (gate)delay characteristics and clock domains than when I'd use schematic entry/building blocks. Schematic entry supports a fairly straightforward left-to-right/top-to-bottom processing workflow; VHDL/Verilog however tend to result in spaghetti-like codeflows (because of the parallel nature of the hardware description), which makes design errors more likely...

That is because the hardware is parallel, and the objective of HDL is to use sequential if's to define parallel and gates. In a schematic you can follow a clock line and see everything it triggers. In hdl you have to find all the always blocks where the clock appears in the text and there has to be an always block for practically every register.

Why would anyone want to look at a block symbol shape, see 4 inputs, and immediately realiz that 4 signals are being and'd. It is more of a challenge to count the if statements.

Unless, someone is able to envision the schematic equivalent in his head while kranking out VHDL, but then using VHDL is more of a nuisance than an advantage.

Remember also that synthesis is in there anxious to throw away the logic that you don't have totally connected so that it can see that it drives an output pin. And it may or may not generate the logic that you wanted. And placement and routing also waste compile time by running while the design is not logically complete. I have been called an idiot for complaining about synthesis throwing logic away that did not drive an output pin because all I was doing was wasting precious power. So I cannot put in incomplete logic to get a resource count for sizing purposes.

VHDL has its place for complicated table driven logic which isn't easily described in functional blocks, but other than that, it makes it more difficult to envision the hardware equivalent than using schematic entry and thus hinders productivity.

Could anyone more proficient than I am in VHDL/Verilog, comment on my assertions above?

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From My POV - drawing schematics becomes extremly unwieldy as designs become more complex (and I have seen large complex designs created with schematics). You could argue you just break it up into smaller chunks, but then you get into a massive heirachy, which can be just as bad.

The great thing about VHDL/Verilog is that it allows you to write more behavioural like code to avoid the stupidly complex diagrams or large hierarchies. Synthesisors and parts are pretty good at laying this into logic on chips at a decent clock speed (if you're working at <100MHz, you can get away with quite long logic chains between registers). I wouldnt want to do a large design with multiplee FIR filters, downsamplers, upsamplers and histograms with just schematics. (and I have tried with simulink). Besides, HDLs have nice methods to tidy away parrallel and identical bits of hardware.

Plus at the end of the day, HDL is standardised text. Schematics have to be visualised.

I do not agree, again, with Tricky's view. A well crafted schematic shows the data- and control- flow in his 'large' design, where now that view only exists in his mind. HDLs may be standardised text, but try reading a large text design ... it may take days before you understand what the hell is going on! Of course here you can resort to RTL-viewer but that is only half-baked in comparison to a proper drafted schematic.

Of course one doesn't use schematic design to build the lowest-level (no belittling intended here) building elements like FIR filters, etc. Because here the HDLs are at their best.