Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

From My POV - drawing schematics becomes extremly unwieldy as designs become more complex (and I have seen large complex designs created with schematics). You could argue you just break it up into smaller chunks, but then you get into a massive heirachy, which can be just as bad.

The great thing about VHDL/Verilog is that it allows you to write more behavioural like code to avoid the stupidly complex diagrams or large hierarchies. Synthesisors and parts are pretty good at laying this into logic on chips at a decent clock speed (if you're working at <100MHz, you can get away with quite long logic chains between registers). I wouldnt want to do a large design with multiplee FIR filters, downsamplers, upsamplers and histograms with just schematics. (and I have tried with simulink). Besides, HDLs have nice methods to tidy away parrallel and identical bits of hardware.

Plus at the end of the day, HDL is standardised text. Schematics have to be visualised.