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And, did Altera drop it for lack of interest? I don't know AHDL and cannot offer any worthwhile comment. Just a logic/systems guy that can put together some code and get it to run. Would like your comments, especially if the similarity is undesirable. Thanks.
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Theres nothing wrong with it as a language. The big problem is lack of support from other vendors (especially as it is Altera HDL).
The problem with the language, and anything similar is that you cant get away from the problem that different vendors have slightly different technologies.
IIRC, altera registers all have an async reset input, while Xilinx prefer sync resets. Also, Altera have a reset and a preset inputs. This comes out in the code like this:
node my_reg : dffe;
my_reg.clk = clk;
my_reg.en = enable;
my_reg.reset = rst;
mr_reg.prn = something;
my_reg.d = input1 & input2;
output = my_reg.q;
etc. etc.
It also has libraries for the multipliers, fifos, memories etc etc that come from vendors. But again the problem is that the interfaces for these differ from vendor to vendor. Writing like this is forcing you to think about the target technology, rather than code that is vendor independent. In VHDL, I can create a RAM that any synethesisor should pick up and place (sorry for the VHDL, but I dont know verilog):
type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0);
signal RAM : ram_t;
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
RAM(wr_addr) <= input;
end if;
read_addr_r <= read_addr;
end if;
end process;
output <= RAM(read_addr_r); --for a registered read.
With this code, I can run it through any synthesisor without modifying the code, because it defines a behaviour that matches the behaviour for a ram, without worrying about different vendors port names.
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