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Altera_Forum
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11 years ago

SCFIFO wrreq and rdreq synchronisation

Hi folks, just a quick question (hopefully), In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi Tricky,

I did consider the dual clock FIFO, but was sort of hoping I could get away without having to bring the async clock from an external source into the FPGA (purely for electrical reasons). And my thinking was that I could resync the wwreq and rdreq signals to my system clock running at twice the async clock, and in the process generate myself a rise edge/ fall edge pulse. Then as long as I spec a suitable hold time for data on the bus I should be OK.

How ever in hindsight, it may be the better option to go for the DCFIFO. Is there anything inherently wrong with my initial idea? Is it workable?

Thanks for your help

deBoogle