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Altera_Forum
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11 years ago

SCFIFO Seems Dead in simulation

Hi everyone,

I am trying to build a LPF, an averaging filter in particular, so I used the FIFO MegaFunction, however, when I simulated the design in ModelSim it turned out that the FIFO is not accepting data and not spitting out neither. The output is stuck on 0 value (Check the screenshot).

I tie up the 'read request' and 'write request' to one, so that it keep writing and reading on every clock edge.... is this correct?

And of course, I added the 'altera_mf' library to ModelSim using this command: 


vsim -L altera_mf -lib work testbench -t 1ps

And no errors on compilation.

Any thoughts guys?

15 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Just a quick note

    you should not read from empty fifo, is your fifo protected

    neither write to full fifo
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I tried everything! With and without protection... keeping rdreq & wrreq stuck on 1 and swapping between them!

    Nothing works! Output is still zero.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I tried everything! With and without protection... keeping rdreq & wrreq stuck on 1 and swapping between them!

    Nothing works! Output is still zero.

    --- Quote End ---

    your diagram is not helpful. is it fifo output you are looking or somewhere further?

    isit zero or undefined?

    are yoiu writing to it?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    No no... fifo output directly... and it is zero.

    I am writing to it... but I don't know whether it is accepting or not.

    Thanks for bearing with me.

    ** UPDATE: I did a separate project contains only SCFIFO and simulated it. Results are disappointing again.. check screenshot in the main post please.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    This is my TestBench: 

    
`timescale 1 ns/ 1ns
module testbench();
  reg clk;
  reg signed  d;
  wire signed  q;
     reg aclr;
    reg fifo_rd = 0;
    reg fifo_wr = 0;
  
  reg signed  romdata ;
  
      initial begin
        romdata = 16'h0000;
        romdata = 16'h0805;
        romdata = 16'h1002;
        romdata = 16'h17ee;
        romdata = 16'h1fc3;
        romdata = 16'h2777;
        romdata = 16'h2f04;
        romdata = 16'h3662;
        romdata = 16'h3d89;
        romdata = 16'h4472;
        romdata = 16'h4b16;
        romdata = 16'h516f;
        romdata = 16'h5776;
        romdata = 16'h5d25;
        romdata = 16'h6276;
        romdata = 16'h6764;
        romdata = 16'h6bea;
        romdata = 16'h7004;
        romdata = 16'h73ad;
        romdata = 16'h76e1;
        romdata = 16'h799e;
        romdata = 16'h7be1;
        romdata = 16'h7da7;
        romdata = 16'h7eef;
        romdata = 16'h7fb7;
        romdata = 16'h7fff;
        romdata = 16'h7fc6;
        romdata = 16'h7f0c;
        romdata = 16'h7dd3;
        romdata = 16'h7c1b;
        romdata = 16'h79e6;
        romdata = 16'h7737;
        romdata = 16'h7410;
        romdata = 16'h7074;
        romdata = 16'h6c67;
        romdata = 16'h67ed;
        romdata = 16'h630a;
        romdata = 16'h5dc4;
        romdata = 16'h5820;
        romdata = 16'h5222;
        romdata = 16'h4bd3;
        romdata = 16'h4537;
        romdata = 16'h3e55;
        romdata = 16'h3735;
        romdata = 16'h2fdd;
        romdata = 16'h2855;
        romdata = 16'h20a5;
        romdata = 16'h18d3;
        romdata = 16'h10e9;
        romdata = 16'h08ee;
        romdata = 16'h00e9;
        romdata = 16'hf8e4;
        romdata = 16'hf0e6;
        romdata = 16'he8f7;
        romdata = 16'he120;
        romdata = 16'hd967;
        romdata = 16'hd1d5;
        romdata = 16'hca72;
        romdata = 16'hc344;
        romdata = 16'hbc54;
        romdata = 16'hb5a7;
        romdata = 16'haf46;
        romdata = 16'ha935;
        romdata = 16'ha37c;
        romdata = 16'h9e20;
        romdata = 16'h9926;
        romdata = 16'h9494;
        romdata = 16'h906e;
        romdata = 16'h8cb8;
        romdata = 16'h8976;
        romdata = 16'h86ab;
        romdata = 16'h845a;
        romdata = 16'h8286;
        romdata = 16'h8130;
        romdata = 16'h8059;
        romdata = 16'h8003;
        romdata = 16'h802d;
        romdata = 16'h80d8;
        romdata = 16'h8203;
        romdata = 16'h83ad;
        romdata = 16'h85d3;
        romdata = 16'h8875;
        romdata = 16'h8b8f;
        romdata = 16'h8f1d;
        romdata = 16'h931e;
        romdata = 16'h978c;
        romdata = 16'h9c63;
        romdata = 16'ha19e;
        romdata = 16'ha738;
        romdata = 16'had2b;
        romdata = 16'hb372;
        romdata = 16'hba05;
        romdata = 16'hc0df;
        romdata = 16'hc7f9;
        romdata = 16'hcf4b;
        romdata = 16'hd6ce;
        romdata = 16'hde7a;
        romdata = 16'he648;
        romdata = 16'hee30;
        romdata = 16'hf629;
    end
    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    
    reg signed  sin1 = 0;
  reg signed  sin2 = 0;
  
  
  //========================================
  initial clk = 0;
    always# 50 clk = ~clk;
    
    reg  index1 = 0;
    always @(posedge clk) begin
      if (index1 == 7'd99)
        index1 <= 7'd0;
      else
        index1 <= index1 + 1;
      
      sin1 <= romdata;
    end
    //=========================================
    reg clk2 = 0;
    always# 5 clk2 = ~clk2;
    
    reg  index2 = 0;
    always @(posedge clk2) begin
     if (index2 == 7'd99) index2 = 0;
     else index2 = index2 + 1;
     
     sin2 <= {{3{romdata}},romdata};
    end
    //==========================================
    wire signed  sum = sin1 + sin2;
    LPF DUT (clk, aclr, sum, fifo_rd, fifo_wr, q);
    
    initial begin
      aclr = 1;
     # 6000 aclr = 0;
    end
    
    initial begin
    # 7000 fifo_wr = 1;
    # 10000 fifo_rd = 1;
    end
    
endmodule

    I have linked the SCFIFO interface to my TOP design interface directly... so sum[12:1] is the data input, fifo_rd & fifo_wr are requests, and q is the output of fifo.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    check you haven't connected aclear instead of clock

    or post your fifo code
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Sir, I am pretty sure that my code is error-free. I tried to simulate a FIFO wrapper... same result! Is there a special procedure to simulate a verilog projects?! I came across a project that simulates FIFO but in VHDL and it worked!

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Given your results, Im pretty sure your code is not error free.

    Why not post the code?

    Is this a standard Megawizard fifo? or some custom fifo?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Given your results, Im pretty sure your code is not error free.

    Why not post the code?

    Is this a standard Megawizard fifo? or some custom fifo?

    --- Quote End ---

    OK, here you go, I am using the standard MegaFunction... I bet that if I used a custom one I wouldn't have all these troubles!

    This is my wrapper module: ff is SCFIFO Megafunction. 

    
module FIFO (aclr, clk, data, rdreq, wrreq, q);
	input aclr;
	input clk;
	input  data;
	input rdreq;
	input wrreq;
	output  q;
	
	wire empty, full;
	wire  used;
	
	fifo_mf ff (aclr, clk, data, rdreq, wrreq, empty, full, q, used);
endmodule

    And here is my Testbench: 

    
`timescale 1ns / 1ns
module tb();
  reg aclr = 0;
  reg clk = 0;
  reg  data = 0;
  reg rdreq = 0;
  reg wrreq = 0;
  wire  q;
  
  FIFO DUT (aclr, clk, data, rdreq, wrreq, q);
  
  always# 10 clk = ~clk;
  
  always# 20 data = data + 1;
  
  initial begin
	 # 40 aclr = 1;
	 # 10 wrreq = 1;
         # 40 rdreq = 1;
  end
endmodule

    And just to disclaim any responsibility, here is my DO script: 

    
vlib work
vlog +acc "tb.v"
vlog +acc "../FIFO.v"
vlog +acc "../fifo_mf.v"
vlog +acc "../fifo_mf_bb.v"
vsim -t 1ps -L altera_mf -lib work tb
view objects
view wave
log -r *
run 1 us

    Now show me the error in my code.