SCFIFO Seems Dead in simulation

This is my TestBench:

`timescale 1 ns/ 1ns
module testbench();
  reg clk;
  reg signed  d;
  wire signed  q;
     reg aclr;
    reg fifo_rd = 0;
    reg fifo_wr = 0;
  
  reg signed  romdata ;
  
      initial begin
        romdata = 16'h0000;
        romdata = 16'h0805;
        romdata = 16'h1002;
        romdata = 16'h17ee;
        romdata = 16'h1fc3;
        romdata = 16'h2777;
        romdata = 16'h2f04;
        romdata = 16'h3662;
        romdata = 16'h3d89;
        romdata = 16'h4472;
        romdata = 16'h4b16;
        romdata = 16'h516f;
        romdata = 16'h5776;
        romdata = 16'h5d25;
        romdata = 16'h6276;
        romdata = 16'h6764;
        romdata = 16'h6bea;
        romdata = 16'h7004;
        romdata = 16'h73ad;
        romdata = 16'h76e1;
        romdata = 16'h799e;
        romdata = 16'h7be1;
        romdata = 16'h7da7;
        romdata = 16'h7eef;
        romdata = 16'h7fb7;
        romdata = 16'h7fff;
        romdata = 16'h7fc6;
        romdata = 16'h7f0c;
        romdata = 16'h7dd3;
        romdata = 16'h7c1b;
        romdata = 16'h79e6;
        romdata = 16'h7737;
        romdata = 16'h7410;
        romdata = 16'h7074;
        romdata = 16'h6c67;
        romdata = 16'h67ed;
        romdata = 16'h630a;
        romdata = 16'h5dc4;
        romdata = 16'h5820;
        romdata = 16'h5222;
        romdata = 16'h4bd3;
        romdata = 16'h4537;
        romdata = 16'h3e55;
        romdata = 16'h3735;
        romdata = 16'h2fdd;
        romdata = 16'h2855;
        romdata = 16'h20a5;
        romdata = 16'h18d3;
        romdata = 16'h10e9;
        romdata = 16'h08ee;
        romdata = 16'h00e9;
        romdata = 16'hf8e4;
        romdata = 16'hf0e6;
        romdata = 16'he8f7;
        romdata = 16'he120;
        romdata = 16'hd967;
        romdata = 16'hd1d5;
        romdata = 16'hca72;
        romdata = 16'hc344;
        romdata = 16'hbc54;
        romdata = 16'hb5a7;
        romdata = 16'haf46;
        romdata = 16'ha935;
        romdata = 16'ha37c;
        romdata = 16'h9e20;
        romdata = 16'h9926;
        romdata = 16'h9494;
        romdata = 16'h906e;
        romdata = 16'h8cb8;
        romdata = 16'h8976;
        romdata = 16'h86ab;
        romdata = 16'h845a;
        romdata = 16'h8286;
        romdata = 16'h8130;
        romdata = 16'h8059;
        romdata = 16'h8003;
        romdata = 16'h802d;
        romdata = 16'h80d8;
        romdata = 16'h8203;
        romdata = 16'h83ad;
        romdata = 16'h85d3;
        romdata = 16'h8875;
        romdata = 16'h8b8f;
        romdata = 16'h8f1d;
        romdata = 16'h931e;
        romdata = 16'h978c;
        romdata = 16'h9c63;
        romdata = 16'ha19e;
        romdata = 16'ha738;
        romdata = 16'had2b;
        romdata = 16'hb372;
        romdata = 16'hba05;
        romdata = 16'hc0df;
        romdata = 16'hc7f9;
        romdata = 16'hcf4b;
        romdata = 16'hd6ce;
        romdata = 16'hde7a;
        romdata = 16'he648;
        romdata = 16'hee30;
        romdata = 16'hf629;
    end
    //~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    
    reg signed  sin1 = 0;
  reg signed  sin2 = 0;
  
  
  //========================================
  initial clk = 0;
    always# 50 clk = ~clk;
    
    reg  index1 = 0;
    always @(posedge clk) begin
      if (index1 == 7'd99)
        index1 <= 7'd0;
      else
        index1 <= index1 + 1;
      
      sin1 <= romdata;
    end
    //=========================================
    reg clk2 = 0;
    always# 5 clk2 = ~clk2;
    
    reg  index2 = 0;
    always @(posedge clk2) begin
     if (index2 == 7'd99) index2 = 0;
     else index2 = index2 + 1;
     
     sin2 <= {{3{romdata}},romdata};
    end
    //==========================================
    wire signed  sum = sin1 + sin2;
    LPF DUT (clk, aclr, sum, fifo_rd, fifo_wr, q);
    
    initial begin
      aclr = 1;
     # 6000 aclr = 0;
    end
    
    initial begin
    # 7000 fifo_wr = 1;
    # 10000 fifo_rd = 1;
    end
    
endmodule