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Altera_Forum's avatar
Altera_Forum
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11 years ago

SCFIFO Seems Dead in simulation

Hi everyone,

I am trying to build a LPF, an averaging filter in particular, so I used the FIFO MegaFunction, however, when I simulated the design in ModelSim it turned out that the FIFO is not accepting data and not spitting out neither. The output is stuck on 0 value (Check the screenshot).

I tie up the 'read request' and 'write request' to one, so that it keep writing and reading on every clock edge.... is this correct?

And of course, I added the 'altera_mf' library to ModelSim using this command: 


vsim -L altera_mf -lib work testbench -t 1ps

And no errors on compilation.

Any thoughts guys?

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I told you you have connected aclr to clk

    --- Quote End ---

    Hhhhhh no I have not... the latter post is for a separate project. And this is how SCFIFO interface is organized! :) I am sure this is not the problem!
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Hhhhhh no I have not... the latter post is for a separate project. And this is how SCFIFO interface is organized! :) I am sure this is not the problem!

    --- Quote End ---

    latter post has conflict of fifo if with first code you posted. Anyway can you see fifo signals in sim (I mean fifo own ports) such as clk, words etc.

    fifos don't go wrong so it is either user error or library issues.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Can you please try a simple simulation with verilog and send it to me? If you have some time of course.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Can you please try a simple simulation with verilog and send it to me? If you have some time of course.

    --- Quote End ---

    I did some work on fifo in verilog.

    If I changed your command to:

    vsim -t 1ps -L altera_mf_ver -lib work testbench

    then it worked (I used dc fifo with same clk connected to both clks but you can try your fifo)

    It is not project based so I can't send any files. Just instantiate dcfifo (I used quartus 14 64bit web edition) and wire it up.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Okay Thank you very much... I was waiting for a good reason to install Quartus 14 although it is waiting in my hard disk :)