Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Can you please try a simple simulation with verilog and send it to me? If you have some time of course. --- Quote End --- I did some work on fifo in verilog. If I changed your command to: vsim -t 1ps -L altera_mf_ver -lib work testbench then it worked (I used dc fifo with same clk connected to both clks but you can try your fifo) It is not project based so I can't send any files. Just instantiate dcfifo (I used quartus 14 64bit web edition) and wire it up.