Hello everyone, Does anyone know if I can insert an s-parameter model of the FPGA power delivery network in Quartus or ModelSim functional/timing simulations? Has anyone done this already? Thank you, Cosmin

Not possible. ModelSim/Quartus are digital logic simulators only. What you require is analog circuit simulation capability; e.g. something like LinearTech LTspiceIV or Cadence PSpice.

--- Quote Start --- Not possible. ModelSim/Quartus are digital logic simulators only. What you require is analog circuit simulation capability; e.g. something like LinearTech LTspiceIV or Cadence PSpice. --- Quote End --- Thank you ak6dn, I don't have experience in FPGA designs but from my other design experience I know that timing margins in logic design depend on propagation delay and clock jitter, which both are very dependent on the self-generated supply noise on the FPGA power rails. Self-generated supply noise depends on the values and locations of decoupling capacitors on the PCB, which is a user dependent decision, so timing models in Quartus II cannot know this information. I assume Quartus II models estimate some (expected) supply noise but the simulator does not know if the estimation is accurate or not because ultimately this depends on the FPGA user. So I am trying to put an s-parameter model of the FPGA PDN (that includes the decoupling capacitors on the PCB) in a circuit simulator to estimate the clock jitter and gate delay variations on FPGA. I have two follow up questions: 1. If I am able to use a Spice simulator (LT Spice for example) and find out the clock jitter on the FPGA due to the dynamic current variation of my specific design, is it a way to insert this jitter value in Quartus II timing analysis or ModelSim functional simulation to see how it affects my timing margin? 2. Does anyone know of any simulation tool, simulation method, or simulation example that uses an s-parameter model of the power delivery network to simulate the timing on an FPGA? Best Wishes, Cosmin

You don't say what device family in particular you are looking at (CycloneIV, V, Max, Stratix, ...) but have you read the detailed electrical data sheets for the family/device you are looking at? They have pretty detailed specs on PLL characteristics (jitter, etc). The 'set_clock_uncertainty' timequest command allows adding additional jitter/uncertainty to a clock rail if necessary. Are you aware of this? (in answer to question one). This would apply to Quartus place/route timing calculations, not modelsim simulation before place/route. How much extra jitter to add however is going to be a guess, unless you can derive the power supply noise to clock jitter transfer function (not easy without the detailed circuit level design of the FPGA). In answer to question two, I have never seen such a tool that uses s-params for FPGA timing. Sounds like a good PhD project. Backing up to square one, why are you so concerned about clock jitter? Is your application some how very critical in this respect?

Thank you ak6dn for the detailed explanation. I am using a Cyclone IV on an evaluation board, and my dynamic power consumption was so high that a few times it reset the FPGA, so I had to reprogram it. Now it does not reset the FPGA. I am now trying to quantify the clock jitter and the propagation delay variation with self-generated supply noise. I come from an IC design background so I tend to think from the circuit perspective. Thank you for the info on "set_clock_uncertainty" feature. Is it a similar feature for signal path delay? Thank you and Best Wishes, Cosmin

I don't believe that "self generated supply noise" is a suitable term to analyze signal integrity problems in FPGA interconnect. The effect is usually described as "ground bounce" generated by switching outputs. It can be modeled in a first order by ground pin inductance. As already explained, FPGA timing analysis doesn't model signal integrity problems specifically, but you can account for it by an increased jitter margin. Tools like Hyperlynx are used for an in-depth analysis of PCB interconnect. From a practician's viewpoint, instead of analyzing ground bounce details, you'll usually try to avoid its effect by using differential signaling for critical signals.

S-parameter model of the power delivery network in Quartus functional simulation

12 Replies

Altera_Forum
Honored Contributor
9 years ago
FPGA reset is a bit more of a basic issue than increased IO jitter. Most likely the core supply falls below the POR trip point. I believe it's more likely caused by a not correctly operating voltage regulator than wrongly placed or insufficient bypass capacitors, but the difference should be obvious when looking at the "noise" waveform.
Altera_Forum
Honored Contributor
9 years ago
Thank you FvM. Yes, it seems to be related to the core supply because after choosing different capacitors the FPGA did not reset anymore. However, what I don't know is "how well" I fixed it and if it is only marginal and will reset again for a future re-compiled version of my design. This is why I am looking for a simulation tool that would take an s-parameter model and somehow provide me the information of "how well" I fixed the core supply.

Forum Discussion

S-parameter model of the power delivery network in Quartus functional simulation

12 Replies

Recent Discussions

About Single Event Upset (SEU)

IP-CXLTYP3DDR-NC

Cyclone 10LP 080 Timing Closure

How to make Questa show delays through gates?

Compiling quartus design of PCIe root port example failing in WSL2