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allenS1's avatar
allenS1
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2 years ago

Running Questa simulation with runtime arguments

Hello there, I'm trying to run a simulation in Questa using a testbench file that utilizes runtime arguments. The testbench file will check these runtime arguments and use the value to control the t...
Simulation
RichardT_altera's avatar
RichardT_altera
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2 years ago

Sorry for the delay due to Chinese New Year.

I noticed that when use $finish, it ends the simulation outright. Conversely, $stop halts the simulation and transitions to interactive mode. So, technically, you can utilize $stop.

Nonetheless, even if you use $finish, Questa typically prompts whether you want to end. Opting for 'no' allows you to stay within the simulation, while selecting 'yes' will exit Questa.

https://stackoverflow.com/questions/2395132/whats-the-difference-between-stop-and-finish-in-verilog

At this point, I suggest consulting Siemens, as they are experts in using the Questa* Core software. (Questa*-Intel® FPGA Starter software editions are a version of Siemens EDA Questa* Core software targeted for Intel FPGA devices.)

Regards,

Richard Tan