Running Questa simulation with runtime arguments

You're correct that the final procedure in a testbench typically runs after the $finish statement in the initial block.

If you're not seeing the $display statements from the final block in the transcript window, there could be a few reasons.

Ensure that the Final block executed in zero times, which implies it can't have any delay, wait, or non-blocking assignments.

See if the final block is instantiated at the correct level of hierarchy in testbench. If it's nested within another block that finished early, it might not get a chance to execute.

Perhaps you can try out a working example to see if it works. If it works, you will need to review the testbench.

Example tb: https://vlsiverify.com/system-verilog/systemverilog-final-block/#google_vignette

Regards,

Richard Tan