Sorry for the late reply, I was locked out of my account and restoring it took a while.
Anyway, if you want to use the host CPU alongside with the FPGA, even though you can also use the CPU as a second OpenCL device, it is likely not the best solution. The main problem will be that if you compile your host code using the Intel OpenCL compiler for FPGAs, the host code will never see your CPU as an OpenCL device. However, if your board manufacturer provides an ICD driver in the BSP, you can compile the host code with Intel's OpenCL compiler for CPUs or AMD's OpenCL compiler and then you can get both the FPGA and the CPU detected. Of course you might lose some functionality specific to FPGAs by using such compilers. What I would do instead is that I would run standard C/C++ code in the host code on the CPU, probably parallelized using MPI or OpenMP, and only use OpenCL for the FPGA. Remember that all OpenCL functions are non-blocking (or have an option for it) and hence, you can easily run C/C++ code on the CPU in parallel with running OpenCL code on the FPGA. You can then use OpenCL events to synchronize the functions running on the two devices.
If, however, you want to use two different FPGA boards, it would depend on whether they belong to same manufacturer or not. If they do, you can easily use them as separate devices since they will be likely using the same PCI-E driver and OpenCL headers. However, for two FPGA boards from different manufacturers, things could get tricky. Again you will likely need to use a compiler different from Intel's OpenCL compiler for FPGAs and have ICD drivers for both boards. Even in that case, you might have trouble getting the boards to work simultaneously due to conflict between the PCI-E drivers of the different manufacturers.
Information on this topic is scarce in the documentation and what I said above is based on my limited experience. I am also still using old versions of the compiler (16.1.2); things might have improved in the newer versions.