Hello, I have been using ModelSim-Altera for my RLT simulations of my FPGA designs. I usually go to Tools->Run Simulation Tool->RTL Simulation and then ModelSim launches, compiles my project, run the sim and displays the data. I have seen others simply open ModelSim, Change Directory and then run a tcl script that compiles the project and runs the testbench simulation. The tcl script is rather lengthy and I was wondering if anyone knows if Quartus can generate the the tcl script for you? I have heard this method is faster and would like to try it out. Can anyone help me? Thanks, Joe

what counts as lengthy? Are they all custom HDL or are they from something like QSYS?

--- Quote Start --- what counts as lengthy? Are they all custom HDL or are they from something like QSYS? --- Quote End --- Tricky, Hello, thanks for responding to my post. I guess I shouldn't have added that in "lengthy", too subjective. I should have just said is there a simple way to generate a script that would include all the library functions needed to compile the project. I guess that within Quartus there must be some files generated when the RTL Sim button is pressed that will produce something you could copy and start building a tcl file. Or, how do other people build the script? Thanks, Joe

Hi joe, You can refer to this video, https://www.youtube.com/watch?v=qznl1c0twy8 It teach you how to use it. Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation)

--- Quote Start --- Hi joe, You can refer to this video, https://www.youtube.com/watch?v=qznl1c0twy8 It teach you how to use it. Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation) --- Quote End --- That wasnt really the question. The question is how to generate the scripts to compile all code in Modelsim WITHOUT using nativelink (ie. from modelsim command line).

Using nativelink is a good start, as user can start modify the script in the .tcl and continue to use it in modelsim. otherwise, you have to write your own scripts Thanks, Best regards, Kentan

RTL Simulation | Altera Community

19 Replies

Altera_Forum
Honored Contributor
8 years ago
Why not learn how to write a testbench in Verilog (or VHDL, as appropriate)? The full verilog language has lots of features that can be used to write complex testbenches (ie, behavioral verilog) that allow one to generate stimulus signals, and check results match expectations. For example, procedural TASKs come to mind as a feature I routinely used.

I fail to see what benefit using TCL scripts would provide over and above using Verilog / SystemVerilog as a language for testbench generation.
Altera_Forum
Honored Contributor
8 years ago
TCL scripts does not include testbench generation, user will still have to write their own testbench unless you use modelsim feature to create one.
Altera_Forum
Honored Contributor
8 years ago
--- Quote Start ---
Why not learn how to write a testbench in Verilog (or VHDL, as appropriate)? The full verilog language has lots of features that can be used to write complex testbenches (ie, behavioral verilog) that allow one to generate stimulus signals, and check results match expectations. For example, procedural TASKs come to mind as a feature I routinely used.

I fail to see what benefit using TCL scripts would provide over and above using Verilog / SystemVerilog as a language for testbench generation.
--- Quote End ---

TCL scripts drive the simulator:
create libraries
compile files
initialise simulation
determine where output logs go.

TCL has nothing to do with the testbench itself, but with actually getting the testbench running.
Altera_Forum
Honored Contributor
8 years ago
Kentan,

Hello, in my modelsim directory I only see msim_transcript which has some comments and some wave commands. I did see a my_counter_run_msim_rtl_Verilog.do file and it has a vlog command which looks like a compiler command. What do you mean "you can drag the message to the top". Are you referring to your youtube clip?

Joe
Altera_Forum
Honored Contributor
8 years ago
Tricky,

Hello, thanks for clarifying that up. Say, are you aware of any simple examples on this topic? Something like the Youtube clip that Kentan did but would include how to write the simple tcl script?

Thanks,
Joe
Altera_Forum
Honored Contributor
8 years ago
Kentan,

Hello, can you please tell me the name of the auto generate script and where to look? Say, this may be a good idea for a Youtube clip just like the one you had on generate a Testbench.

Joe
Altera_Forum
Honored Contributor
8 years ago
Hi Joe,

If I remember correctly, it should be the *.do files. What you can do is when the modelsim launch, scroll to the top of your message. You will see some command being use like do *.do.

Thanks,
Best regards,
Kentan
(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor
8 years ago
Kentan,

Hello, thanks for information. I found the file and will try to do a simple project and a script to run in ModelSim. If I have problems you probably see a post.

Joe
Altera_Forum
Honored Contributor
8 years ago
I got it working. In the simulation/modelsim directory there is a file called "my_counter_run_msim_rtl_Verilog.do ". I simply opened ModelSim and changed the directory to the directory of the file and then typed "do my_counter_run_msim_rtl_Verilog.do" and my simulation ran. Thanks everyone for your comments.

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RTL Simulation

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