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Altera_Forum
Honored Contributor
Honored ContributorRTL Simulation
Hello, I have been using ModelSim-Altera for my RLT simulations of my FPGA designs. I usually go to Tools->Run Simulation Tool->RTL Simulation and then ModelSim launches, compiles my project, run the...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Why not learn how to write a testbench in Verilog (or VHDL, as appropriate)? The full verilog language has lots of features that can be used to write complex testbenches (ie, behavioral verilog) that allow one to generate stimulus signals, and check results match expectations. For example, procedural TASKs come to mind as a feature I routinely used. I fail to see what benefit using TCL scripts would provide over and above using Verilog / SystemVerilog as a language for testbench generation. --- Quote End --- TCL scripts drive the simulator: create libraries compile files initialise simulation determine where output logs go. TCL has nothing to do with the testbench itself, but with actually getting the testbench running.
