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Why not learn how to write a testbench in Verilog (or VHDL, as appropriate)? The full verilog language has lots of features that can be used to write complex testbenches (ie, behavioral verilog) that allow one to generate stimulus signals, and check results match expectations. For example, procedural TASKs come to mind as a feature I routinely used.
I fail to see what benefit using TCL scripts would provide over and above using Verilog / SystemVerilog as a language for testbench generation.
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TCL scripts drive the simulator:
create libraries
compile files
initialise simulation
determine where output logs go.
TCL has nothing to do with the testbench itself, but with actually getting the testbench running.
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