Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
Try "derive_pll_clocks".
See: http://quartushelp.altera.com/15.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ext_ver_1.0_cmd_derive_pll_clocks.htm Cheers, Alex - Altera_Forum
Honored Contributor
Hi Alex
actually derive_pll_clocks automatically creates the generated clocks. what I need is to retrieve those derived clocks to use it in the sdc file like the following: set_max_delay 10 [ get_clocks <generated clocks from a giving refclk1> to [get_clocks <generated clocks from another giving refclk2>