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Honored Contributor
Honored ContributorRestricted Fmax
Hello.
I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. 1) As a result of simulation of any projects (both simple and complex) with the clock frequency greater than or equal 320 MHz system simulation output port is shown constant zero. At frequencies less than 320 MHz simulation system is working properly. Restricted Fmax = 420MHz. As a simulation system used ModelSim Altera Starter Edition. When using the Quartus II Simulator that is no problem. Tell me how to solve this problem? 2) My project is a pipeline scheme - the multiplication of two n-bit numbers. The scheme consists of n-bit registers A and B of the multiplicand and the multiplier, a group of n elements AND, and vertical adder SM. I need to know how long it takes from the receipt of the input data into the input registers scheme to get full results at the output. How do I estimate this interval using Quartus?2 Replies
Altera_Forum1. What is your actual clock frequency? what is the actual data throughput needed? why bother testing for these extreme clock speeds when your real clock speed is probably much slower
2. Just count the number of registers in the pipeline and it will take that many clocks.- Altera_Forum
Restricted Fmax isn't what the achievable clock frequency is. It is based on hardware limitations, such as IO pin speeds.
Timequest will tell you the actually achievable Fmax for each timing corner - which is based on your design, speed grade, device family.
