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Honored Contributor
Honored ContributorRestricted Fmax
Hello. I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II. 1) As a result of simulation of any projects (both simple and complex) with the clock frequency ...
Altera_ForumHonored Contributor
Honored Contributor1. What is your actual clock frequency? what is the actual data throughput needed? why bother testing for these extreme clock speeds when your real clock speed is probably much slower
2. Just count the number of registers in the pipeline and it will take that many clocks.
