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Daniel99
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8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
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Daniel99's avatar
Daniel99
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8 months ago

I felt it was time to do some tests on the bench.

I hooked up an RF signal generator and a spectrum analyzer to a 10CL006 in C8 grade that I had on a PCB from an earlier project. By first using an LVCMOS (clock) input pin for my design with a divide by four block and an LVCMOS output, I could give it my 500 MHz and see a nice 125 MHz coming out.

In fact, I could go above 1.2 GHz (!), and still see it dividing by four without any problems. The limitation here mostly seemed to be the CMOS input sensitivity since I could not get a nice CMOS square wave but had an AC coupled sine biased at 1.2V.

When changing the input to LVDS it got much more sensitive and I could now give it almost exactly 2000 MHz before the logic failed and started to give me a frequency out that differed from the input divided by four.

Really impressing!