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Daniel99's avatar
Daniel99
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8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
Daniel99's avatar
Daniel99
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8 months ago

Thank you again Kenny and Frank.

There is definitely some confusion here and I also realize I have misunderstood table 19.

But if we are now back to that the restricted Fmax I see with my 500 MHz clock is not due to LVDS speed limitation but due to a minimum period for the LE blocks, I would like to revert to my first question: Why do I get 438 MHz for C6 and not the 500 MHz stated in table 20?

What is the definition of Clock tree performance, in table 20?