Forum Discussion
Daniel99
New Contributor
New ContributorRestricted Fmax due to minimum period
I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Daniel99New Contributor
New ContributorI'll answer my own question: Table 29 lists these frequencies for LVDS receiver.
But where are the corresponding max frequency specs for other I/O-standards?
