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Daniel99's avatar
Daniel99
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8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
Daniel99's avatar
Daniel99
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8 months ago

Thank you Kenny! This makes perfect sense. However, if Quartus was a little more verbose about the restricted Fmax and mentioned the LVDS frequency limitation in this case it would of course be easier to understand.

The numbers you mention for I/O frequency restriction vs. the different speed grades, I cannot find in the device datasheet. Are they listed somewhere else?

I'll try your design!