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Daniel99's avatar
Daniel99
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1 year ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
KennyT_altera's avatar
KennyT_altera
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1 year ago

Do you mind to attached your design for me to view? User cannot usually ignore the restricted Fmax.


  • Daniel99's avatar
    Daniel99
    Icon for New Contributor rankNew Contributor
    1 year ago

    Of course. It is a very simple design just to test this. Hereby attached.

    I can add that my main goal is to be able to feed a 500 MHz clock into the FPGA and directly divide it down to a lower frequency. I don't really intend to clock anything else than a divider at this high rate.

    Thanks.