/RESET signal in VHDL

I'm back with this.

I think it works , my led is on / off /on

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity reset is

Port (

clk_in : in STD_LOGIC;

reset_n: out STD_LOGIC

);

end reset;

architecture Behavioral of reset is

signal temporal: STD_LOGIC:='1';

signal cycle: integer range 0 to 2 := 0;

signal counter : integer range 0 to 10000000 := 0;

begin

frequency_divider: process (clk_in) begin

if rising_edge(clk_in) then

if (counter = 10000000) and (cycle /= 2) then

temporal <= NOT(temporal);

counter <= 0;

cycle <= cycle + 1;

else

counter <= counter + 1;

end if;

end if;

end process;

reset_n <= temporal;

end Behavioral;

Now I need to find good time for a valid /RESET signal.