Honored Contributori want to simulation the design at post-fit stage.
but global reset does not have any effect when reset is set. the initial value was ignored, all of register was set to 0. is that a bug of quartus? can i work around it?
Honored Contributorare you sure its not a bug in your code. please post it.
Honored Contributori don't think it is a bug of code,
it was been proved by hardware test, it will restore the RESET_VALUE at the start point. below is the part which act abnormal in simulation.
1.
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output DataOut;
reg DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
DataOut<=#1 RESET_VALUE;
end
else if(SyncReset)
begin
DataOut<=#1 RESET_VALUE;
end
else if(Write) // write
begin
DataOut<=#1 DataIn;
end
end
endmodule // Register
==================================
2.
//here is the module initialization code
//'ETH_PACKETLEN_DEF_0 was defined as 8'hee.
eth_register# (`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
(
.DataIn (DataIn),
.DataOut (PACKETLENOut),
.Write (PACKETLEN_Wr),
.Clk (Busclk),
.Reset (Reset),
.SyncReset (1'b0)
);
======================
3.
cycloneii_routing_wire inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_DATAIN_routing_wire_inst (
.datain(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_a17_combout),
.dataout(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_DATAIN_driver));
cycloneii_routing_wire inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ACLR_routing_wire_inst (
.datain(inst_aeth_A_aReset_aclkctrl_outclk),
.dataout(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ACLR_driver));
cycloneii_routing_wire inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ENA_routing_wire_inst (
.datain(inst_aeth_A_aethreg1_aPACKETLEN_Wr_a2_a_a4_combout),
.dataout(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ENA_driver));
// atom is at LCFF_X34_Y19_N9
cycloneii_lcell_ff inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a(
.clk(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_CLK_driver),
.datain(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_DATAIN_driver),
.sdata(gnd),
.aclr(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ACLR_driver),
.sclr(gnd),
.sload(gnd),
.ena(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut_a6_a_ENA_driver),
.devclrn(devclrn),
.devpor(devpor),
.regout(inst_aeth_A_aethreg1_aPACKETLEN_0_aDataOut));
With recent FPGAs, e.g. Cyclone III, asynchronous set will always use aclr and "not pushback" to invert the value, please consult the Quartus software manunal for details. In gate level simulation, you'll possibly see a wrong value for the register, because not pushback isn't considered. But the value should appear correctly in derived signals.
Honored Contributorplease give me the reference link on "not pushback", i cant catch what it means.
i searched the quartus handbook for it, but still have no idea.Honored Contributori got that, does it means that i must turn this option off in order to get the correct initial environment after reset?
Honored ContributorWithout the "NOT Gate Push-Back" option, Quartus can't synthesize registers with asynchronous set.
Please notice, that I only assume, that the option is the reason why you see a wrong register content. The more important question is, if the register's initial value is correctly seen by the design.Honored Contributor
