reset signal does not restore value in post-fit simulation.

--- Quote Start ---

Without the "NOT Gate Push-Back" option, Quartus can't synthesize registers with asynchronous set.

Please notice, that I only assume, that the option is the reason why you see a wrong register content. The more important question is, if the register's initial value is correctly seen by the design.

--- Quote End ---

the reset signal works correct in the design, but the failure of initial value loading makes it difficult to perform the timing simulation.