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Altera_Forum's avatar
Altera_Forum
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15 years ago

reset signal does not restore value in post-fit simulation.

i want to simulation the design at post-fit stage. but global reset does not have any effect when reset is set. the initial value was ignored, all of register was set to 0. is that a bug...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

With recent FPGAs, e.g. Cyclone III, asynchronous set will always use aclr and "not pushback" to invert the value, please consult the Quartus software manunal for details. In gate level simulation, you'll possibly see a wrong value for the register, because not pushback isn't considered. But the value should appear correctly in derived signals.