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First a small remark
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Try to avoid that non standard library as much as possible. There are unfortunately several VHDL books that still use it, but the recommended library for arithmetic is ieee.numeric_std.all. Logic_unsigned will cause you problems the day you will also want to use signed logic in the same architecture, and doesn't live well with numeric_std.
Now for you problem I'd definitely check the reset and clock signals first. Are you sure your reset signal is active high? Is your clock on the correct pin? You can use signaltap to record your reset signal, using "clock" as a clock. Then if you don't have a clock you'll get a warning/error from Signaltap, and if you do you will be able to check the polarity of the reset signal. If both look ok then you can begin and checking the other signals from your state machine.
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Hi daixiwen,
Thanks for introducing the signaltap function to me..
Both u n tricky are a great help,learnt something from u guys!
Honored Contributor
