Request for help in VHDL troubleshooting

Assuming you're creating a waveform to drive a DUT (design under test), then your waveform IS your testbench.

You run your testbench and DUT in a simulator and you can veiw the waveform in the wave window in the normal way. You need to use a proper simulator (like modelsim) to do HDL simulation. The quartus simulator is not very powerful and only simulates the compiled netlist via waveforms which is very slow compared to simulating the HDL directly.

Another advantage of using HDL as the testbench is you can generate far more complex input stimulus, and output practically anything to text files.