Request for help in VHDL troubleshooting

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There are plenty of tutorial websites. A testbench is some VHDL code that stimulates your design under test. It doesnt have to be synthesisable and you can do plenty of "programming" like things. For example, to generate a clock, you can write:

signal clk : std_logic := '0';
....
clk <= not clk after 5 ns; -- 100 Mhz clock

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Geezz..Thanks!

Having problem understanding the testbench thing.

What is the difference between a testbench and simulation with waveform?