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Honored Contributor
Honored ContributorRequest for help in VHDL troubleshooting
Hi all, I am a new to programming of VHDL to FPGA. Recently tried experimenting with a code from a book and during simulation, it was functioning perfectly. However after i programmed into...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- There are plenty of tutorial websites. A testbench is some VHDL code that stimulates your design under test. It doesnt have to be synthesisable and you can do plenty of "programming" like things. For example, to generate a clock, you can write:
signal clk : std_logic := '0';
....
clk <= not clk after 5 ns; -- 100 Mhz clock
