Honored ContributorHi all,
I am a Xilinx user and want to release my IP core for Altera users also. But I do not want to send the verilog source to my customers. I do not use any Xilinx/Altera IP cores. It's just plain verilog. Is it possible to convert the verilog source to an altera netlist ? How is it done ? How can my customer use it in his design ? Thanks Tom
Honored ContributorAssignments -> Settings -> Incremental Compilation and check "Automatically export .qxp". This will write out a Quartus eXport Partition file. You probably want to check on the Options box below it and only export Post-Synthesis netlist. This way it will be re-placed and routed in the user's design. You could also use Synplify, which writes out a .vqm. (I think Mentor's synthesis tool writes out an EDIF).
Honored ContributorSorry to hear that you are a Xilinx user :-) Depending on what family you are targeting, you can output a .vqm file from Quartus II (under Settings -> Compilation Process Settings) which will output a Verilog obfuscated file that can be read in by Quartus II. It is family specific because the output instantiates specific WYSIWYG primitives for the targeted family. Other than that, Altera does have a tool that will encrypt your Verilog code that will be automatically decrypted by Quartus II during compilation. In order to get this tool however, you may have to become an Altera IP partner. You may want to contact someone at the San Jose factory regarding this.
Honored ContributorHonored ContributorYou need a full licence to do incremental compilation. So unless you get a full licence, you'll have to distrubute the source code.
