Release IP without source

Sorry to hear that you are a Xilinx user :-) Depending on what family you are targeting, you can output a .vqm file from Quartus II (under Settings -> Compilation Process Settings) which will output a Verilog obfuscated file that can be read in by Quartus II. It is family specific because the output instantiates specific WYSIWYG primitives for the targeted family. Other than that, Altera does have a tool that will encrypt your Verilog code that will be automatically decrypted by Quartus II during compilation. In order to get this tool however, you may have to become an Altera IP partner. You may want to contact someone at the San Jose factory regarding this.