Forum Discussion
GOMEZ_IT
Occasional Contributor
Occasional Contributorreg~feeder REMOVE?
Good morning.
I'm trying to make 2-register synchronizers for the metstability problem on asynchronous signals.
Quartus automatically inserts the LUT between one register and another which calls regx...
GOMEZ_ITOccasional Contributor
Occasional ContributorI don't need to achieve better results.
I just wanted to understand if there are any constraints or attributes to pass to the
synthesizer to connect the registers as desired.
Let's just say it's for educational purposes only
FvM
Super Contributor
Super ContributorHi,
Quartus provides quite limited features to manually control fitting and routing results. Review this recent thread discussing a similar problem https://community.intel.com/t5/Intel-Quartus-Prime-Software/Altera-Register-Chain/m-p/1497097
Consider that Quartus is designed to fit complex circuits in an optimal way. You probably should take it as granted that it has no features to command a specific implementation of trivial circuits.
Even if you use wysiwyg_lcell low primitives to describe your circuit, it won't be necessarily exactly implemented as coded. The register cascade data path isn't even present in the lcell primitive.
