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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

reg~feeder REMOVE?

Good morning. I'm trying to make 2-register synchronizers for the metstability problem on asynchronous signals. Quartus automatically inserts the LUT between one register and another which calls regx...
Compilation
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

between the output of the LUT (combout) and the input of the FLOP (datain) there is a switch.
Can this switch not be switched to exclude the LUT?

as far as I understand, the datapath you are referring to has a specific dedication for SLOAD function. There's an optional register chain datapath, but I don't know if it's available in the present situation.

Basically fitter is selecting the best available datapath automatically, particularly considering timing constraints. Why do you worry about fitter results?

GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
I don't need to achieve better results. 
I just wanted to understand if there are any constraints or attributes to pass to the 
synthesizer to connect the registers as desired.
Let's just say it's for educational purposes only
  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,
    Quartus provides quite limited features to manually control fitting and routing results. Review this recent thread discussing a similar problem https://community.intel.com/t5/Intel-Quartus-Prime-Software/Altera-Register-Chain/m-p/1497097

    Consider that Quartus is designed to fit complex circuits in an optimal way. You probably should take it as granted that it has no features to command a specific implementation of trivial circuits.

    Even if you use wysiwyg_lcell low primitives to describe your circuit, it won't be necessarily exactly implemented as coded. The register cascade data path isn't even present in the lcell primitive.