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Altera_Forum's avatar
Altera_Forum
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10 years ago

Reconfigurable generic interface

Dear forum members

In my current project using a (DE2-115), I have the following problem. I use a component "sub", with the following entity: 

ENTITY sub ISGENERIC(
      Parameter : INTEGER);
PORT(
      clk : IN STD_LOGIC;
      rst_n : IN STD_LOGIC);
END sub;

In this component, the "Parameter" is used to load timing registers, which are needed to generate a signal of a certain length.

The component above is instanciated in another component "top", where I have a Constant, specifiying the value of "Parameter". 

CONSTANT TIME_A : INTEGER := 15;

However, in the component "top", I receive data from a pc (through RS232 communication), namely, the timing value, which is intended to load the timers in the component "sub".

So I've learned that a Signal cannot be used to supply a Generic value. I'm looking for an alternative solution to solve this problem.

I've tried to use the type Signal for "Parameter" and pass it on as one, but then I encountered some problems loading the timer registers properly.

Are Generic values intended to be reconfigurable in the first place?

Thanks for your answer.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    You cannot connect it like this.

    Imagine the parameter dictates the number of pins on your device - you cannot expect the number of pins to change in real time.

    So you need to create a register inside your sub component that stores the timing value that is written from the RS232. This will be at some address of some kind, so you'll need an address decoder. And then you'll need some sort of protocol to understand register writes from the RS232.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for your answer. I now understand why the initial approach can't work (It's always hard to imagine as a VHDL greenhorn). I've tried again to introduce the type Signal for "Parameter" and it appears to be working now. I am just wondering about the initialization, isn't it critical to initialize a register with a Signal (default value)?

    For example like this (Code in the architecture of the "sub" component): 

    counter_d : INTEGER;
counter_q : INTEGER := Parameter; --Default register value

    (Note that counter_q is updated by the value counter_d, synchronously with the clock signal)

    Thanks again