Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThanks for your answer. I now understand why the initial approach can't work (It's always hard to imagine as a VHDL greenhorn). I've tried again to introduce the type Signal for "Parameter" and it appears to be working now. I am just wondering about the initialization, isn't it critical to initialize a register with a Signal (default value)?
For example like this (Code in the architecture of the "sub" component):counter_d : INTEGER;
counter_q : INTEGER := Parameter; --Default register value (Note that counter_q is updated by the value counter_d, synchronously with the clock signal) Thanks again