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Altera_Forum's avatar
Altera_Forum
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10 years ago

Reconfigurable generic interface

Dear forum members In my current project using a (DE2-115), I have the following problem. I use a component "sub", with the following entity: ENTITY sub ISGENERIC( Parameter : INTE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks for your answer. I now understand why the initial approach can't work (It's always hard to imagine as a VHDL greenhorn). I've tried again to introduce the type Signal for "Parameter" and it appears to be working now. I am just wondering about the initialization, isn't it critical to initialize a register with a Signal (default value)?

For example like this (Code in the architecture of the "sub" component): 

counter_d : INTEGER;
counter_q : INTEGER := Parameter; --Default register value

(Note that counter_q is updated by the value counter_d, synchronously with the clock signal)

Thanks again