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Altera_Forum
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11 years ago

Real numbers on altera fpga de5

Hi all,

The problem that I m facing is that I have to perform some operations that are mostly logarithms exponentials multiplications division and additions on Real numbers.

From the simulation point of view there were no problems but now when I try to synthetize it I obtain an error message. I m using math_real library.

Are there any smart solutions in order to deal with Real numbers instead of write its own floating point unit??

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The real type is not synthesisable at all. So forget about using it on an FPGA.

    Altera provides floating point cores for all FP operations. But why do you need floating point? FPGAs are not designed for floating point, so they take up a large amount of logic and have high latency to keep the clock frequencies high. Fixed point is much better because it is basically integer arithmatic that FPGAs are designed for.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I know but we want to compare the proejct on the fpga with later on the realization of the asic keeping the same structures. Do you know if all this operation like exp and log and mul of floating points are supported by the fp cores?

    Thanks for the reply
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    If logic count is a concern but not latency, create an IEEE754 compliant FPU with only basic add, mult, and divide.

    CORDIC can be applied to calculate almost all commonly used math functions iteratively.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    If neither speed nor accuracy (especuially of the trig functions) is required, write an emulator for the old sinclair scientific calculator!

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I would prefer in order to accelerate all the design use a fp core from altera. Do you think that is so bad use it ?? I mean in terms of perfomances is it so slow??

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Its not slow. With a decent level of pipelining you should get high FMAX. But why do you need floating point? is fixed point unnacceptable?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You are perfectly right but I need to follow some design constrains ( in the asic realization there will be a floating point unit) and so they want one also on the fpga.