Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou are perfectly right but I need to follow some design constrains ( in the asic realization there will be a floating point unit) and so they want one also on the fpga.
You are perfectly right but I need to follow some design constrains ( in the asic realization there will be a floating point unit) and so they want one also on the fpga.