reading video using vhdl

Thanks for your reply, i'm a very big beginner.. my experience only last 3 months in vhdl.. as what you have mentioned is not recommended for me what should i follow then??

let me tell you what i've did so far:

first: i've converted each frame into txt file

second: built ROM component where i saved file name in

third: read this file inorder to calculate mean value.. and so on

i'm having a question on what i did

is there any function that declares end of line since there is endfile() that declares if i've reached end of file

as i've noticed that when i use readline() i comes back with the first value in that line only and i should calculate mean over all of the file's value

one more question

i've been trying this statement

file mean_calc : text open read_mode is file_nm_str_sig;

where file_nm_str_sig is of string type & changes when ROM address changes

it was compiled successfuly with warning => (Initial value of "mean_calc" depends on value of signal "file_nm_str_sig")

but when i started simulation i got this error =>(Failed to open VHDL file "" in rb mode.)

although file_nm_str_sig is already having a value

is there any work arround to do that??

thanks,

Niveen..

I think you're getting a bit muddled

FileIO is ONLY meant for testing/simulation. You cannot synthesise file IO in a real circuit. And even more annoyingly Quartus will not let you use textio to read values into a ROM. So the question is - do you want this to work on a board, or are you happy with simulation?

yes sir you are right.. i'm too muddled..

i'm really appreciating your guidance and advice..

of course i will be happy with simulation first as its my first complete application.. and ofcourse i want it to work on a board..

i thought that i should simulate the application then find a way for synthesis..

it hasn't come to my mind to built my application synthesisable from the begining and these are the only tools with me..

it seems that i'm going in a wrong path.. but this is what my thought brings me to..

when you told me its not that easy for beginner.. i thought that this is the right way for me as a beginner

but its ok..

which one do you recommend to me???

one more thing plz..

can i write or draw something to any of the video frames and re-store it again???

thanks alot,

Niveen..

You can get a little bit of mileage out of using ModelSim TCL commands to load and store RAM contents in data files. So your test bench TCL script would initialize the RAM from a data file, start your VHDL simulation, then write the output back to a data file upon completion.

When you have something synthesized, you could do something like a similar script in system-console via JTAG to load/store the memory contents.

I personally find it easier to write a PC program to convert images into .hex / .mif / .dat memory file formats than it is to write corresponding text parsers in HDL.

thanks ted..

its first time to deal with files, images...everything..

so i'm converting images to .txt using matlab.. will check out how to make it .hex ...

would you plz tell me what will the different when dealing within vhdl coding..

sorry for my experience lack, but i'm self-learner even with no mentor.. :(

thanks,

Niveen..

This task (loading and storing image data from a disk file on your PC) is throw-away work which is only useful for simulation and not useful for synthesis.

I prefer to do such throw-away work using TCL scripts or PC software (C/C++/perl) if I can.

The main benefit to this approach is that the VHDL you end up with is almost entirely ready for synthesis. Of course, this is assuming that your VHDL block intends to operate against a frame buffer in a RAM somewhere.

So, overall, it is a simplification of the VHDL you need to write, at the expense of having to learn how to automate your simulation tool a little bit.