This task (loading and storing image data from a disk file on your PC) is throw-away work which is only useful for simulation and not useful for synthesis.
I prefer to do such throw-away work using TCL scripts or PC software (C/C++/perl) if I can.
The main benefit to this approach is that the VHDL you end up with is almost entirely ready for synthesis. Of course, this is assuming that your VHDL block intends to operate against a frame buffer in a RAM somewhere.
So, overall, it is a simplification of the VHDL you need to write, at the expense of having to learn how to automate your simulation tool a little bit.