reading video using vhdl

You can get a little bit of mileage out of using ModelSim TCL commands to load and store RAM contents in data files. So your test bench TCL script would initialize the RAM from a data file, start your VHDL simulation, then write the output back to a data file upon completion.

When you have something synthesized, you could do something like a similar script in system-console via JTAG to load/store the memory contents.

I personally find it easier to write a PC program to convert images into .hex / .mif / .dat memory file formats than it is to write corresponding text parsers in HDL.