Thanks for your reply, i'm a very big beginner.. my experience only last 3 months in vhdl.. as what you have mentioned is not recommended for me what should i follow then??
let me tell you what i've did so far:
first: i've converted each frame into txt file
second: built ROM component where i saved file name in
third: read this file inorder to calculate mean value.. and so on
i'm having a question on what i did
is there any function that declares end of line since there is endfile() that declares if i've reached end of file
as i've noticed that when i use readline() i comes back with the first value in that line only and i should calculate mean over all of the file's value
one more question
i've been trying this statement
file mean_calc : text open read_mode is file_nm_str_sig;
where file_nm_str_sig is of string type & changes when ROM address changes
it was compiled successfuly with warning => (Initial value of "mean_calc" depends on value of signal "file_nm_str_sig")
but when i started simulation i got this error =>(Failed to open VHDL file "" in rb mode.)
although file_nm_str_sig is already having a value
is there any work arround to do that??
thanks,
Niveen..